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词汇表（Glossary）

  • BAR: base address register.
  • PCI configuration space.
  • sba: system bus address.

PCI

PCI configurtation space

PCI设备有一组被称为configuratin space的寄存器，并且PCI Express引入了Extended configuration space。configuration space寄存器被映射到memory locations。
驱动设备和诊断软件必须要有权限访问configuration space，操作系统通常使用APIs来授权访问设备configuration space。

PCI configuration space有两种类型的Header（64 bytes）：

Header Type 0x0

Register Offset Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0
0x0 0x0 Device ID Vendor ID
0x1 0x4 Status Command
0x2 0x8 Class code Subclass Prog IF Revision ID
0x3 0xC BIST Header type Latency Timer Cache Line Size
0x4 0x10 Base address #0 (BAR0)
0x5 0x14 Base address #1 (BAR1)
0x6 0x18 Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number
0x7 0x1C Secondary Status I/O Limit I/O Base
0x8 0x20 Memory Limit Memory Base
0x9 0x24 Prefetchable Memory Limit Prefetchable Memory Base
0xA 0x28 Prefetchable Base Upper 32 Bits
0xB 0x2C Prefetchable Limit Upper 32 Bits
0xC 0x30 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
0xD 0x34 Reserved Capability Pointer
0xE 0x38 Expansion ROM base address
0xF 0x3C Bridge Control Interrupt PIN Interrupt Line

Header Type 0x1

Register Offset Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0
0x0 0x0 Device ID Vendor ID
0x1 0x4 Status Command
0x2 0x8 Class code Subclass Prog IF Revision ID
0x3 0xC BIST Header type Latency Timer Cache Line Size
0x4 0x10 Base address #0 (BAR0)
0x5 0x14 Base address #1 (BAR1)
0x6 0x18 Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number
0x7 0x1C Secondary Status I/O Limit I/O Base
0x8 0x20 Memory Limit Memory Base
0x9 0x24 Prefetchable Memory Limit Prefetchable Memory Base
0xA 0x28 Prefetchable Base Upper 32 Bits
0xB 0x2C Prefetchable Limit Upper 32 Bits
0xC 0x30 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
0xD 0x34 Reserved Capability Pointer
0xE 0x38 Expansion ROM base address
0xF 0x3C Bridge Control Interrupt PIN Interrupt Line 
BAR0
Memory-mapped I/O (MMIO) registers
BAR1
Device memory windows.
BAR2/3
Complementary space of BAR1.
BAR5
I/O port.
BAR6
PCI ROM.

Commands

lspci

Interpreting the output of lspci

参考